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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. flexbanktm is a trademark of fujitsu limited, japan. embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc 64 mbit flash memory and 16 mbit pseudo sram stacked multi-chip package (mcp) preliminary information august 2002 mcp features ? power supply voltage of 2.7 to 3.1 volt high performance: - flash access time as fast as 70 ns - psram access time as fast as 80 ns package: 65-ball fbga operating temperature: ?30c to +85c flash memory features 0.16 m proce ss technology simultaneous read/write operations (dual bank) flexbank tm architecture - bank a : 8 mbit ( 8 kb x 8 and 64 kb x 15) - bank b : 24 mbit (64 kb x 48) - bank c : 24 mbit (64 kb x 48) - bank d : 8 mbit ( 8 kb x 8 and 64 kb x 15) - two virtual banks are chosen from the combination of four physical banks (refer to "example of virtual banks combination table" and simultaneous operation table" in flexible sector-erase architecture on flash memory) - host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. - read-while-erase - read-while-program single 3.0 v read, program, and erase - minimized system level power requirements minimum 100,000 program/erase cycles sector erase architecture - sixteen 4 kword and one hundred twenty-six 32 kword sectors in word - any combination of sectors can be concurrently erased - supports full chip erase hidden rom (hi-rom) region - 256 byte of hi-rom, accessible through a new "hi- rom enable" command sequence - factory serialized and protected to provide a secure electronic serial number (esn) wp /acc input pin - at v il , allows protection of ?outermost? 2 8 kbytes on both ends of boot sectors, regardless of sector protection/unprotection status - at v ih , allows removal of boot sector protection - at v acc , program time will be reduced by 40 % embedded erase tm algorithms - automatically preprograms and erases the chip or any sector embedded program tm algorithms - automatically writes and verifies data at specified address data polling and toggle bit feature for detection of program or erase cycle completion ready/busy output (ry/ by ) - hardware method for detection of program or erase cycle completion automatic sleep mode - when addresses remain stable, the device automatically switches itself to low power mode. low v cc f write inhibit 2.5 v program suspend/resume - suspends the program operation to allow a read in another byte erase suspend/resume - suspends the erase operation to allow a read data and/or program in another sector within the same device psram features power dissipation: - operating : 20 ma max - standby : 70 a max - power down : 10 a max power down control by ce2r byte write control : lb (dq 7 -dq 0 ), ub (dq 15 -dq 8 ) 4 words address access capability
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? pin descriptions a0-a19 address inputs, common a20-a21 address inputs, flash dq0-dq15 data inputs/outputs, common reset hardware reset pin/acceleration, flash ce1 r,ce2r chip enable, psram ry/ by ready/busy output, flash open drain output ce f chip enable, flash oe output enable, common we write enable, common lb lower-byte control, psram ub upper-byte control, psram wp /acc write protect/acceleration, flash ry/ by ready/busy output nc no internal connection vccf device power supply, flash gnd device ground, common vccr device power, psram pin configuration (64 mb flash and 16 mb psram) package code: d 65 ball fbga (top view) (9.00 mm x 9.00 mm body, 0.8 mm ball pitch) a b c d e f g h j k 10 9 8 7 6 5 4 3 2 1 nc nc nc nc a11 a8 we wp /acc lb a7 nc a15 a12 a19 ce2r reset ub a6 a3 a21 a13 a9 a20 ry/ by a18 a5 a2 nc a14 a10 a17 a4 a16 nc dq6 dq1 gnd a0 vccf dq15 dq13 dq4 dq3 dq9 oe ce f gnd dq7 dq12 vccr vccf dq10 dq0 ce 1r dq14 dq5 nc dq11 dq2 dq8 nc nc nc nc common flash only psram onl y a1
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? logic symbol mcp block diagram gnd gnd vcc f ry/ by 16-mbit static psram 64-mbit flash memory dq15-dq0 a21-a0 wp /acc reset ce f lb ub we oe ce1 r ce2r dq15-dq0 a19-a0 v ccr a21-a0 dq15-dq0 a21-a0 ce f ce1 r ce2r oe we wp /acc reset ub lb dq15-dq0 22 x16 ry/ by
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash memory block diagram state control & command register reset we ce wp /acc dq15-dq0 a21-a0 a21-a0 a21-a0 a21-a0 a21-a0 lower bank address upper bank address y-decoder latches and control logic lower bank upper bank x-decoder y-decoder latches and control logic x-decoder status control dq15-dq0 dq15-dq0 dq15-dq0 oe oe v cc gnd
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? full standby h h h x x x x high-z high-z h x output disable (3) h l x h h x x high-z high-z h x l h x h h x x high-z high-z h x read from flash (4) lh xl h x x d out d out hx write to flash l h x h l x x d in d in hx read from psram (5) hl hl h x x d out d out hx write to psram l l d in d in h l h h l h l high-z d in hx lh d in high-z temporary sector x x x x x x x x x v id x group unprotection (6) flash hardware x h h x x x x high-z high-z l x reset boot block sector write x x x x x x x x x x l protection psram power down (8) xxlxxxxx xx x legend : l = vil, h = vih, x = vil or vih. see ?dc characteristics? for voltage levels. notes: 1. other operations not indicated in this table are prohibited. 2. do not apply ce f = vil, ce 1r = vil and ce2r = vih all at once. 3. psram output disable condition should not be kept longer than 1 ms. 4. we can be vil if oe is vil, oe at vih initiates the write operations. 5. psram byte control at read operation is not supported. 6. also used for the extended sector group protections. 7. protects ?outermost? 2 8 kbytes (4 words) on both ends of the boot block sectors. 8. power down mode can be entered from standby state and all dq pins are in high-z state. device bus operations operation (1,2) ce ce ce ce ce f ce1 ce1 ce1 ce1 ce1 r ce2r oe oe oe oe oe we we we we we lb lb lb lb lb s ub ub ub ub ub sdq 7- dq 0 dq 15 -dq 8 reset reset reset reset reset wp wp wp wp wp /acc (7)
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flexible sector-erase architecture on flash memory bank sector bank sector type address k-word address type address k-word address banka sa0 4 000000h bankb sa36 32 0e8000h banka sa1 4 001000h bankb sa37 32 0f0000h banka sa2 4 002000h bankb sa38 32 0f8000h banka sa3 4 003000h bankb sa39 32 100000h banka sa4 4 004000h bankb sa40 32 108000h banka sa5 4 005000h bankb sa41 32 110000h banka sa6 4 006000h bankb sa42 32 118000h banka sa7 4 007000h bankb sa43 32 120000h banka sa8 32 008000h bankb sa44 32 128000h banka sa9 32 010000h bankb sa45 32 130000h banka sa10 32 018000h bankb sa46 32 138000h banka sa11 32 020000h bankb sa47 32 140000h banka sa12 32 028000h bankb sa48 32 148000h banka sa13 32 030000h bankb sa49 32 150000h banka sa14 32 038000h bankb sa50 32 158000h banka sa15 32 040000h bankb sa51 32 160000h banka sa16 32 048000h bankb sa52 32 168000h banka sa17 32 050000h bankb sa53 32 170000h banka sa18 32 058000h bankb sa54 32 178000h banka sa19 32 060000h bankb sa55 32 180000h banka sa20 32 068000h bankb sa56 32 188000h banka sa21 32 070000h bankb sa57 32 190000h banka sa22 32 078000h bankb sa58 32 198000h bankb sa23 32 080000h bankb sa59 32 1a0000h bankb sa24 32 088000h bankb sa60 32 1a8000h bankb sa25 32 090000h bankb sa61 32 1b0000h bankb sa26 32 098000h bankb sa62 32 1b8000h bankb sa27 32 0a0000h bankb sa63 32 1c0000h bankb sa28 32 0a8000h bankb sa64 32 1c8000h bankb sa29 32 0b0000h bankb sa65 32 1d0000h bankb sa30 32 0b8000h bankb sa66 32 1d8000h bankb sa31 32 0c0000h bankb sa67 32 1e0000h bankb sa32 32 0c8000h bankb sa68 32 1e8000h bankb sa33 32 0d0000h bankb sa69 32 1f0000h bankb sa34 32 0d8000h bankb sa70 32 1f8000h bankb sa35 32 0e0000h bankc sa71 32 200000h
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flexible sector-erase architecture on flash memory (continued) bank sector bank sector type address k-word address type address k-word address bankc sa72 32 208000h bankc sa107 32 320000h bankc sa73 32 210000h bankc sa108 32 328000h bankc sa74 32 218000h bankc sa109 32 330000h bankc sa75 32 220000h bankc sa110 32 338000h bankc sa76 32 228000h bankc sa111 32 340000h bankc sa77 32 230000h bankc sa112 32 348000h bankc sa78 32 238000h bankc sa113 32 350000h bankc sa79 32 240000h bankc sa114 32 358000h bankc sa80 32 248000h bankc sa115 32 360000h bankc sa81 32 250000h bankc sa116 32 368000h bankc sa82 32 258000h bankc sa117 32 370000h bankc sa83 32 260000h bankc sa118 32 378000h bankc sa84 32 268000h bankd sa119 32 380000h bankc sa85 32 270000h bankd sa120 32 388000h bankc sa86 32 278000h bankd sa121 32 390000h bankc sa87 32 280000h bankd sa122 32 398000h bankc sa88 32 288000h bankd sa123 32 3a0000h bankc sa89 32 290000h bankd sa124 32 3a8000h bankc sa90 32 298000h bankd sa125 32 3b0000h bankc sa91 32 2a0000h bankd sa126 32 3b8000h bankc sa92 32 2a8000h bankd sa127 32 3c0000h bankc sa93 32 2b0000h bankd sa128 32 3c8000h bankc sa94 32 2b8000h bankd sa129 32 3d0000h bankc sa95 32 2c0000h bankd sa130 32 3d8000h bankc sa96 32 2c8000h bankd sa131 32 3e0000h bankc sa97 32 2d0000h bankd sa132 32 3e8000h bankc sa98 32 2d8000h bankd sa133 32 3f0000h bankc sa99 32 2e0000h bankd sa134 4 3f8000h bankc sa100 32 2e8000h bankd sa135 4 3f9000h bankc sa101 32 2f0000h bankd sa136 4 3fa000h bankc sa102 32 2f8000h bankd sa137 4 3fb000h bankc sa103 32 300000h bankd sa138 4 3fc000h bankc sa104 32 308000h bankd sa139 4 3fd000h bankc sa105 32 310000h bankd sa140 4 3fe000h bankc sa106 32 318000h bankd sa141 4 3ff000h
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flexbank tm architecture table bank 1 bank 2 bank split volume combination volume combination 1 8 mbit bank a 56 mbit bank b, c, d 2 24 mbit bank b 40 mbit bank a, c, d 3 24 mbit bank c 40 mbit bank a, b, d 4 8 mbit bank d 56 mbit bank a, b, c example of virtual banks combination table bank 1 bank 2 bank split volume combination sector size volume combination sector size 1 8 mbit bank a 8x4 kword 56 mbit bank b, c, d 8x4 kword 15x32 kword 111x32 kword 2 16 mbit bank a,d 16x4 kword 48 mbit bank b,c 96x32 kword 30x32 kword 3 24 mbit bank b 48x32 kword 40 mbit bank a, c, d 16x4 kword 78x32 kword 4 32 mbit bank a,b 8x4 kword 32 mbit bank c,d 8x4 kword 63x32 kword 63x32 kword notes: 1) when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for example, if erasing is taking place at both bank a and bank b, neither bank a nor bank b is read out. they would output the sequence flag once they were selected. meanwhile the system would get to read from either bank c or bank d.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? simultaneous operation table case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode (1) 5 autoselect mode read mode 6 program mode read mode 7 erase mode (1) read mode note: 1) by writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. 2) bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks , bank a, bank b, bank c and bank d. bank address (ba) means to specify each of the banks.
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? sector address table bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank a sa0 0000000000 000000h to 000fffh bank a sa1 0000000001 001000h to 001fffh bank a sa2 0000000010 002000h to 002fffh bank a sa3 0000000011 003000h to 003fffh bank a sa4 0000000100 004000h to 004fffh bank a sa5 0000000101 005000h to 005fffh bank a sa6 0000000110 006000h to 006fffh bank a sa7 0000000111 007000h to 007fffh bank a sa8 0000001xxx 008000h to 00ffffh bank a sa9 0000010xxx 010000h to 017fffh bank a sa10 0000011xxx 018000h to 01ffffh bank a sa11 0000100xxx 020000h to 027fffh bank a sa12 0000101xxx 028000h to 02ffffh bank a sa13 0000110xxx 030000h to 037fffh bank a sa14 0000111xxx 038000h to 03ffffh bank a sa15 0001000xxx 040000h to 047fffh bank a sa16 0001001xxx 048000h to 04ffffh bank a sa17 0001010xxx 050000h to 057fffh bank a sa18 0001011xxx 058000h to 05ffffh bank a sa19 0001100xxx 060000h to 067fffh bank a sa20 0001101xxx 068000h to 06ffffh bank a sa21 0001110xxx 070000h to 077fffh bank a sa22 0001111xxx 078000h to 07ffffh bank b sa23 0010000xxx 080000h to 087fffh bank b sa24 0010001xxx 088000h to 08ffffh bank b sa25 0010010xxx 090000h to 097fffh bank b sa26 0010011xxx 098000h to 09ffffh bank b sa27 0010100xxx 0a0000h to 0a7fffh bank b sa28 0010101xxx 0a8000h to 0affffh bank b sa29 0010110xxx 0b0000h to 0b7fffh bank b sa30 0010111xxx 0b8000h to 0bffffh bank b sa31 0011000xxx 0c0000h to 0c7fffh bank b sa32 0011001xxx 0c8000h to 0cffffh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? sector address table (continued) bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank b sa33 0011010xxx 0d0000h to 0d7fffh bank b sa34 0011011xxx 0d8000h to 0dffffh bank b sa35 0011100xxx 0e0000h to 0e7fffh bank b sa36 0011101xxx 0e8000h to 0effffh bank b sa37 0011110xxx 0f0000h to 0f7fffh bank b sa38 0011111xxx 0f8000h to 0fffffh bank b sa39 0100000xxx 100000h to 107fffh bank b sa40 0100001xxx 108000h to 10ffffh bank b sa41 0100010xxx 110000h to 117fffh bank b sa42 0100011xxx 118000h to 11ffffh bank b sa43 0100100xxx 120000h to 127fffh bank b sa44 0100101xxx 128000h to 12ffffh bank b sa45 0100110xxx 130000h to 137fffh bank b sa46 0100111xxx 138000h to 13ffffh bank b sa47 0101000xxx 140000h to 147fffh bank b sa48 0101001xxx 148000h to 14ffffh bank b sa49 0101010xxx 150000h to 157fffh bank b sa50 0101011xxx 158000h to 15ffffh bank b sa51 0101100xxx 160000h to 167fffh bank b sa52 0101101xxx 168000h to 16ffffh bank b sa53 0101110xxx 170000h to 177fffh bank b sa54 0101111xxx 178000h to 17ffffh bank b sa55 0110000xxx 180000h to 187fffh bank b sa56 0110001xxx 188000h to 18ffffh bank b sa57 0110010xxx 190000h to 197fffh bank b sa58 0110011xxx 198000h to 19ffffh bank b sa59 0110100xxx 1a0000h to 1a7fffh bank b sa60 0110101xxx 1a8000h to 1affffh bank b sa61 0110110xxx 1b0000h to 1b7fffh bank b sa62 0110111xxx 1b8000h to 1bffffh bank b sa63 0111000xxx 1c0000h to 1c7fffh bank b sa64 0111001xxx 1c8000h to 1cffffh bank b sa65 0111010xxx 1d0000h to 1d7fffh
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? sector address table (continued) bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank b sa66 0111011xxx 1d8000h to 1dffffh bank b sa67 0111100xxx 1e0000h to 1e7fffh bank b sa68 0111101xxx 1e8000h to 1effffh bank b sa69 0111110xxx 1f0000h to 1f7fffh bank b sa70 0111111xxx 1f8000h to 1fffffh bank c sa71 1000000xxx 200000h to 207fffh bank c sa72 1000001xxx 208000h to 20ffffh bank c sa73 1000010xxx 210000h to 217fffh bank c sa74 1000011xxx 218000h to 21ffffh bank c sa75 1000100xxx 220000h to 227fffh bank c sa76 1000101xxx 228000h to 22ffffh bank c sa77 1000110xxx 230000h to 237fffh bank c sa78 1000111xxx 238000h to 23ffffh bank c sa79 1001000xxx 240000h to 247fffh bank c sa80 1001001xxx 248000h to 24ffffh bank c sa81 1001010xxx 250000h to 257fffh bank c sa82 1001011xxx 258000h to 25ffffh bank c sa83 1001100xxx 260000h to 267fffh bank c sa84 1001101xxx 268000h to 26ffffh bank c sa85 1001110xxx 270000h to 277fffh bank c sa86 1001111xxx 278000h to 27ffffh bank c sa87 1010000xxx 280000h to 287fffh bank c sa88 1010001xxx 288000h to 28ffffh bank c sa89 1010010xxx 290000h to 297fffh bank c sa90 1010011xxx 298000h to 29ffffh bank c sa91 1010100xxx 2a0000h to 2a7fffh bank c sa92 1010101xxx 2a8000h to 2affffh bank c sa93 1010110xxx 2b0000h to 2b7fffh bank c sa94 1010111xxx 2b8000h to 2bffffh bank c sa95 1011000xxx 2c0000h to 2c7fffh bank c sa96 1011001xxx 2c8000h to 2cffffh bank c sa97 1011010xxx 2d0000h to 2d7fffh bank c sa98 1011011xxx 2d8000h to 2dffffh bank c sa99 1011100xxx 2e0000h to 2e7fffh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? sector address table (continued) bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank c sa100 1011101xxx 2e8000h to 2effffh bank c sa101 1011110xxx 2f0000h to 2f7fffh bank c sa102 1011111xxx 2f8000h to 2fffffh bank c sa103 1100000xxx 300000h to 307fffh bank c sa104 1100001xxx 308000h to 30ffffh bank c sa105 1100010xxx 310000h to 317fffh bank c sa106 1100011xxx 318000h to 31ffffh bank c sa107 1100100xxx 320000h to 327fffh bank c sa108 1100101xxx 328000h to 32ffffh bank c sa109 1100110xxx 330000h to 337fffh bank c sa110 1100111xxx 338000h to 33ffffh bank c sa111 1101000xxx 340000h to 347fffh bank c sa112 1101001xxx 348000h to 34ffffh bank c sa113 1101010xxx 350000h to 357fffh bank c sa114 1101011xxx 358000h to 35ffffh bank c sa115 1101100xxx 360000h to 367fffh bank c sa116 1101101xxx 368000h to 36ffffh bank c sa117 1101110xxx 370000h to 377fffh bank c sa118 1101111xxx 378000h to 37ffffh bank d sa119 1110000xxx 380000h to 387fffh bank d sa120 1110001xxx 388000h to 38ffffh bank d sa121 1110010xxx 390000h to 397fffh bank d sa122 1110011xxx 398000h to 39ffffh bank d sa123 1110100xxx 3a0000h to 3a7fffh bank d sa124 1110101xxx 3a8000h to 3affffh bank d sa125 1110110xxx 3b0000h to 3b7fffh bank d sa126 1110111xxx 3b8000h to 3bffffh bank d sa127 1111000xxx 3c0000h to 3c7fffh bank d sa128 1111001xxx 3c8000h to 3cffffh bank d sa129 1111010xxx 3d0000h to 3d7fffh bank d sa130 1111011xxx 3d8000h to 3dffffh bank d sa131 1111100xxx 3e0000h to 3e7fffh bank d sa132 1111101xxx 3e8000h to 3effffh bank d sa133 1111110xxx 3f0000h to 3f7fffh bank d sa134 1111111000 3f8000h to 3f8fffh bank d sa135 1111111001 3f9000h to 3f9fffh bank d sa136 1111111010 3fa000h to 3fafffh bank d sa137 1111111011 3fb000h to 3fbfffh bank d sa138 1111111100 3fc000h to 3fcfffh bank d sa139 1111111101 3fd000h to 3fdfffh bank d sa140 1111111110 3fe000h to 3fefffh bank d sa141 1111111111 3ff000h to 3fffffh
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? sector address group table sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0 000000000 sa0 sga1 0 000000001 sa1 sga2 0 000000010 sa2 sga3 0 000000011 sa3 sga4 0 000000100 sa4 sga5 0 000000101 sa5 sga6 0 000000110 sa6 sga7 0 000000111 sa7 01 sga8 0 000010xxx sa8 to sa10 11 sga9 0 0001 xxxxx sa11 to sa14 sga10 0 0010 xxxxx sa15 to sa18 sga11 0 0011 xxxxx sa19 to sa22 sga12 0 0100 xxxxx sa23 to sa26 sga13 0 0101 xxxxx sa27 to sa30 sga14 0 0110 xxxxx sa31 to sa34 sga15 0 0111 xxxxx sa35 to sa38 sga16 0 1000 xxxxx sa39 to sa42 sga17 0 1001 xxxxx sa43 to sa46 sga18 0 1010 xxxxx sa47 to sa50 sga19 0 1011 xxxxx sa51 to sa54 sga20 0 1100 xxxxx sa55 to sa58 sga21 0 1101 xxxxx sa59 to sa62 sga22 0 1110 xxxxx sa63 to sa66 sga23 0 1111 xxxxx sa67 to sa70 sga24 1 0000 xxxxx sa71 to sa74 sga25 1 0001 xxxxx sa75 to sa78 sga26 1 0010 xxxxx sa79 to sa82 sga27 1 0011 xxxxx sa83 to sa86 sga28 1 0100 xxxxx sa87 to sa90 sga29 1 0101 xxxxx sa91 to sa94 sga30 1 0110 xxxxx sa95 to sa98 sga31 1 0111 xxxxx sa99 to sa102 sga32 1 1000 xxxxx sa103 to sa106
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash memory autoselect codes table type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufacture's code ba lllll 04h device code ba l l l l h 227eh extended device ba l h h h l 2202h code (2) ba l h h h h 2201h sector group sector group l l l h l 01h (1) protection address legend: l = vil, h = vih. see ?n dc characteristics? for voltage levels. notes: 1. outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. 2. a read cycle at address (ba) 01h outputs device code. when 227eh was output, this indicates that there will require two additional codes, called extended device codes. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh. . sector address group table (continued) sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga33 1 1001 xxxxx sa107 to sa110 sga34 1 1010 xxxxx sa111 to sa114 sga35 1 1011 xxxxx sa115 to sa118 sga36 1 1100 xxxxx sa119 to sa122 sga37 1 1101 xxxxx sa123 to sa126 sga38 1 1110 xxxxx sa127 to sa130 00 sga39 1 111101xxx sa131 to sa133 10 sga40 1 111111000 sa134 sga41 1 111111001 sa135 sga42 1 111111010 sa136 sga43 1 111111011 sa137 sga44 1 111111100 sa138 sga45 1 111111101 sa139 sga46 1 111111110 sa140 sga47 1 111111111 sa141
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash memory command definitions notes: 1. both read/reset commands are functionally equivalent, resetting the device to the read mode. 2. this command is valid during fast mode. 3. this command is valid while reset = v id 4. the valid address is a6 to a0. 5. this command is valid during hi-rom mode. 6. the data ?00h? is also acceptable. command sequence 2 1 3 4 4 bus write cycle req'd first bus second bus third bus fourth bus fifth bus sixth bus cycle write cycle write cycle read/write cycle cycle data read / reset (1) flash program (2) erase resume data data addr. addr. addr. addr. data addr. data addr. data read / reset (1) spa 60h spa ? spa ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 55h ? ? ? ? ? ? ? ? ? ? ? f0h aah 30h ? ra ? ? ? 55h aah f0h ? rd ? ? ? sd ? ? 40h 88h ba xxxh 30h a0h 90h 98h 55h set to fast mode (2) autoselect program program suspend program resume sector erase erase suspend query (4) hi-rom entry 90h pa ? ? 55h b0h pd a0h ? ? 3 3 4 1 extended sector group protection (3) reset from flash mode (2) hi-rom exit (5) 555h aah 2aah 55h 555h a0h 00h 1 hi-rom program (5) chip erase 2 3 4 1 1 6 6 1 xxxh 555h 555h 555h ba ba 555h 555h 555h 555h (ba) 55h aah aah 2aah 555h 2aah (ba) 555h 2aah 555h ? ? ? ? ? ? ? ?? ? ? ? ? ? ? aah ? ? ? ? aah b0h 2aah 2aah 55h 55h 555h 555h 80h 80h 555h 555h aah aah 2aah 2aah 55h 55h 55h 555h sa 10h 30h ? ? ?? ? ? ? ? ? ? ba b0h ? ? ?? ? ? ? ? ? ? 60h 555h aah 2aah 55h 555h 20h xxxh pa pd ?? ? ? ? ? ? ? ba xxxh (6) f0h ? ? ?? ? ? ? ? ? ? ? ? ? ? 2aah 2aah 55h 555h 555h (hrba) 90h xxxh pd ?? ? ? ? ? ? ? ? ? (hra) pa
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash memory command definitions (continued) pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. spa = sector group address to be protected. set sector group address and (a6, a3, a2, a1, a0) = (0, 0, 0, 1, 0). sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hi-rom area : 000000h to 00007fh hrba = bank address of the hi-rom area (a21 = a20 = a19 = vil) the system should generate the following address patterns : 555h or 2aah to addresses a10 to a0 both read/reset commands are functionally equivalent, resetting the device to the read mode. command combinations not described in ?flash memory command definitions? are illegal. notes: address bits a21 to a11 = x = ?h? or ?l? for all address commands except or program address (pa), sector address (sa) , and bank address (ba) , and sector group address (spa) . bus operations are defined in "device bus operations?. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a21, a20, a19, a18, a17, a16, a15, a14, a13, and a12 will uniquely select any sector. ba = bank address (a21, a20, a19) rd = data read from location ra during read operation.
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? absolute maximum ratings rating symbol parameter min. max. unit tstg storage temperature ?55 +125 c t a ambient temperature with power applied ?30 +85 c v in voltage with respect to ground all pins (1,2) ?0.3 v cc f + 0.3 v v out voltage with respect to ground all pins (1,2) ?0.3 v cc r + 0.3 v v cc fv cc f supply (1) ?0.2 +3.6 v v cc rv cc r supply (1,3) -0.2 +3.6 v v in reset (1,3) -0.5 +13.0 v v acc wp /acc (1,4) ?0.5 +10.5 v notes: 1. voltage is defined on the basis of gnd = gnd = 0 v. 2. minimum dc voltage on input or i/o pins is -0.3 v. during voltage transitions, input or i/o pins may undershoot gnd to -1.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is vccf + 0.3 v or vccr + 0.3 v. during voltage transitions, input or i/o pins may overshoot to vccf + 1.0 v or vccr + 1.0 v for periods of up to 5 ns. 3. minimum dc input voltage on reset pin is -0.5 v. during voltage transitions, reset pin may undershoot gnd to -2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (vin-vccf or vccr) does not exceed 9.0 v. maximum dc input voltage on reset pin is +13.0 v that may overshoot to +14.0 v for periods of up to 20 ns. 4. minimum dc input voltage on wp/acc pin is -0.5 v. during voltage transitions, wp/acc pin may undershoot gnd to -2.0 v for periods of up to 20 ns. maximum dc input voltage on wp/acc pin is +10.5 v which may overshoot to +10.5 v for periods of up to 20 ns, when vccf is applied. 5. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions rating symbol parameter min. max. unit t a ambient temperature ?30 +85 c v cc fv cc f supply voltages ?2.7 +3.1 v v cc rv cc r supply voltages ?2.7 +3.1 v note: voltage is defined on the basis of gnd = gnd = 0 v.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? dc characteristics symbol parameter test conditions min. typ. max. unit i li input leakage v in =gnd to v cc f, v cc r -1.0 ? +1.0 a i lo output leakage v out =gnd to v cc f, v cc r -1.0 ? +1.0 a i lit reset inputs v cc f=v cc f max., ? ? 35 a leakage current reset = 12.5v i cc 1f flash vcc (1) ce f=v il , oe =v ih tcycle = 5mhz ? ? 18 ma active current (read) tcycle = 1mhz ? ? 4 ma i cc 2f flash vcc active (2) ce f=v il ,??35ma current(program/erase) oe =v ih i cc 3f flash vcc active (5) ce f=v il ,??53ma current oe =v ih (read-while-program) i cc 4f flash vcc active (5) ce f=v il ,??53ma current oe =v ih (read-while-erase) i cc 5f flash vcc active ce f=v il ,??40ma current oe =v ih (erase-suspend-program) i acc wp /acc acceleration v cc f = vcc max, ? ? 20 ma program current wp /acc = v acc max i cc 1r psram vcc active v cc r = vccr max, trc / twc = min ? 15 20 ma current ce 1r=v il , ce2r=v ih , v in =v ih or v il , trc / twc = 1 s ? 2.5 3.0 ma i out =0 ma i sb 1f flash vcc v cc f = vccf max, ce f= v cc f + 0.3v, ? 1 5 a standby current reset = v cc f + 0.3v , wp /acc = v cc f + 0.3v i sb 2f flash vcc v cc f = vccf max, reset = gnd + 0.3v, ? 1 5 a standby current wp /acc = v cc f + 0.3v ( reset ) i sb 3f flash vcc (3) v cc f = vcc max., ce f, = gnd + 0.3v, ? 1 5 a current reset = v cc f + 0.3v, (automatic sleep mode) wp /acc = v cc f + 0.3v, v in = v cc f + 0.3v or gnd + 0.3v i sb r psram vcc standby v cc r = vccr max, ce1 r = ce2 r = v in , ? 0.5 1 ma current v in =v ih or v il , i out =0 ma i sb 1r psram vcc standby v cc r = vccr max, ce1 r v cc r -0.2v, ? ? 70 a current ce2r v cc r -0.2v, v in 0.2 v or v in v cc r -0.2v i out =0 ma i sb 2r psram vcc standby v cc r = vccr max, ce1 r v cc r -0.2v, ? ? 5 ma current (6) ce2r v cc r -0.2v, v in cycle time = t rc min, i out = 0 ma
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? dc characteristics (continued) symbol parameter test conditions min. max. unit i pd r psram v cc power v cc r = v cc r max., ? 10 a down current v in v cc f - 0.2 v or v in 0.2 v ce2r 0.2 v, i out = 0 ma v il input low level -0.3 0.5 v v ih input high level (flash) 2.0 v cc f + 0.3 v v ih input high level (psram) 2.2 v cc r + 0.3 v v id voltage for autoselect 11.5 12.5 v and sector protection ( reset ) (4) v acc voltage for wp /acc 8.5 9.5 v sector protection/unprotection and program acceleration (4) v ol output low level v cc r = v cc r min., v ccs =v ccs min. ? 0.4 v (psram) i ol = 1.0 ma v oh output high level v cc r = v cc r min., v ccs =v ccs min. 2.2 ? v (psram) i oh = -0.5 ma v ol output low level v cc f = v cc f min., v ccs =v ccs min. ? 0.45 v (flash) i ol = 4.0 ma v oh output high level v cc f = v cc f min., v ccs =v ccs min. v cc f - 0.4 ? v (flash) i oh = -0.1 ma v lko flash low vccf 2.3 2.5 v lock-out voltage notes: 1. icc current listed includes both the dc operating current and the frequency dependent component. 2. icc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remains stable for 150 ns. 4. applicable for only vccf applying. 5. embedded algorithm (program or erase) is in progress. (@5 mhz) 6. isb2 r depends on vin cycle time. please refer to appendix a. .
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? timing diagram for alternating psram to flash ac characteristics - ce ce ce ce ce timing parameter symbol condition min max unit ce f recover time t ccr ?0?ns ce f hold time t chold ?3?ns ce 1r high to we invalid time for t chwx ?20?ns standby entry ce f ce 1r ce2r t ccr t ccr t ccr t ccr t chwx t chold we
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? jedec standard parameter symbol symbol cond ition min max unit read cycle time t avav t rc 70 ? ns address to output delay t avqv t acc ce f = v il , oe = v il ?70 ns chip enable to output delay t elqv t ce oe = v il ?70 ns output enable to output delay t glqv t oe ?30 ns chip enable to output high-z t ehqz t df ?25 ns output enable to output high-z t ghqz t df ?25 ns output hold time from addresses, t axqx t oh 0? ns ce f or oe , whichever occures first reset pin low to read mode ? t ready ?20 s flash read only operations characteristics test conditions : output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or vccf timing measurement reference level input : vccf/2 output : vccf/2
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash read cycle address dq ce f oe we address stable output valid high-z high-z t oeh t rc t oe t df t ce t acc
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash hardware reset reset reset reset reset / read operation timing diagram address dq ce f reset address stable output valid high-z t rc t acc t rh t ce t rh t rp t oh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? write/erase/program operations jedec standard parameter symbol symbol min typ max unit write cycle time t avav t wc 70 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low ? t aso 12 ?? ns during toggle bit polling address hold time t wlax t ah 45 ?? ns address hold time from ce or ? t aht 0 ?? ns oe high during toggle bit polling data setup time t dvwh t ds 30 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read ? t oeh 0 ?? ns output enable hold time ? t oeh 10 ?? ns toggle and data polling ce high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write ( oe to ce )t ghwl t ghwl 0 ?? ns read recover time before write ( oe to we )t ghel t ghel 0 ?? ns we setup time (cef to we) t elwl t ws 0 ?? ns ce setup time (we to ce) t wlel t cs 0 ?? ns we hold time (ce to we) t wheh t wh 0 ?? ns ce hold time (we to ce) t ehwh t ch 0 ?? ns write pulse width t wlwh t wph 35 ?? ns ce f pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wph 25 ?? ns ce pulse width high t ehel t cph 25 ?? ns programming operation t whwh 1t whwh 1 ? 10 ? s sector erase operation (1) t whwh 2t whwh 2 ? 0.2 ? s v cc setup time ? t vcs 50 ?? s rise time to v id (2) ? t vidr 500 ?? ns rise time to v id (3) ? t vaccr 500 ?? ns voltage transition time (2) ? t vlht 4 ?? s write pulse width (2) ? t wpp 100 ?? s
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? write/erase/program operations (continued) jedec standard parameter symbol symbol min typ max unit oe setup time to we active (2) ? t oesp 4 ?? s ce setup time to we active (2) ? t csp 4 ?? s recover time from ry/ by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns reset high level period before read ? t rh 200 ?? ns program/erase valid to ry/ by delay ? t busy ?? 90 ns delay time from embedded output enable ? t eoe ?? 70 ns erase time-out time ? t tow 50 ?? s erase suspend transition time ? t spd ?? 20 s notes: 1. does not include preprogramming time. 2. for sector group protection operation. 3. for accelerated program operation.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash write cycle ( we control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. address dq ce f oe we a0h dq 7 dout pa 555h pa data polling pd dout t as 3rd bus cycle t ah t rc t oe t ce t oh t df t ds t dh t whwh1 t cs t ch t ghwl t wp t wph t wc
28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash write cycle ( cef control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. address dq ce f oe we aoh dq 7 dout pa 555h pa data polling pd t as 3rd bus cycle t ah t wc t ds t dh t whwh1 t ws t wh t ghel t cp t cph
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash ac waveforms chip/sector erase operations notes: 1 . sa is the sector address for sector erase. address = 555h for chip erase. address dq ce f oe we 55h 10h/ 30h vccf 55h aah 80h aah 555h 2aah 555h 555h 2aah sa (1) 30h for sector erase t wc t as t ah t sc t ch t wp t wph t vcs t ghwl t ds t dh
30 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash ac waveforms for data data data data data polling during embedded algorithm operations notes: 1 . dq 7 = valid data (the device has completed the embedded operation.) data in dq 0 /dq 6 cef oe we ry/ by dq data in dq 7 dq 0 to dq 6 = output flag dq 0 to dq 6 valid data dq 7 = valid data t df t busy t whwh1 or 2 t oe t eoe t oeh t ce t ch high - z high - z (1)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash ac waveforms for toggle bit during embedded algorithm operations notes: 1 . dq6 stops toggling (the device has completed the embedded operation). toggle toggle toggle toggle outpu t data data data data valid data address dq 6 /dq 2 ce f oe we t dh t busy t oeh t oe ry/ by t ce t oeh t oeph t ceph t aht t aso t aht t as (1)
32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash back-to-back read/write timing diagram note: 1. this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1; ba2: address of bank 2. address dq cef oe we ba1 ba1 ba1 t rc t as t ah t acc t ce ba2 (555h) ba2 (pa) ba2 (pa) read command read command read read valid valid valid valid valid output input output input output status t wc t rc t wc t rc t rc t ds t dh t df t df t oeh (pd) t ghwl t wp (a0h) t oe t ceph t aht t as
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 33 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash ry/ by by by by by timing diagram during write/erase operations flash reset, reset, reset, reset, reset, ry/ by by by by by timing diagram we ce f ry/ by the rising edge of the last write pulse entire programming or erase operations t busy we reset ry/ by t ready t rp t rb
34 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash extended sector group protection notes: 1 . spax : sector group address to be protected, spay : next group sector address to be protected, time-out: time-out window = 250 s (min) reset address a 6 , a 3 a 2 , a 0 a1 ce f oe we data vccf 60h 60h 40h 01h 60h spax spay spax time-out t vcs t vidr t vlht t wc t wp t oe t wc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 35 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram read operations value parameter symbol min. max. unit read cycle time t rc 90 ? ns chip enable access time (1,3) t ce ? 80 ns output enable access time (1) t oe ? 45 ns chip enable access time (1,4) t aa ? 80 ns output data hold time (1) t oh 5 ? ns ce 1r low to output low-z (2) t clz 5 ? ns oe low to output low-z (2) t olz 0 ? ns ce 1r high to output high-z (2) t chz ? 30 ns oe high to output high-z (2) t ohz ? 25 ns address setup time to ce 1r low (5) t asc -5 ? ns address setup time to oe (3,6) t aso 45 ? ns address setup time to oe (7) t aso ( abs )10 ? ns address invalid time (4) t ax ? 5 ns ce 1r low to address hold time (4) t clah 90 ? ns oe low to address hold time (4,8) t olah 45 ? ns ce 1r high to address hold time t chah -5 ? ns oe high to address hold time t ohah -5 ? ns ce 1r low to oe low delaytime (4,6,8,9) t clol 45 1000 ns oe low to ce 1r high delaytime (8) t olch 45 ? ns ce 1r high pulse width t cp 20 ? ns oe high pulse width (6,8,9) t op 45 1000 ns oe high pulse width (7) t op ( abs )20 ? ns notes: 1. the output load is 30 pf. 2. the output load is 5 pf. 3. the t ce is applicable if oe is brought to low before ce 1r goes low and is also applicable if actual value of both or either t aso or t clol is shorter than specified value. 4. applicable only to a0 and a1 when both ce 1r and oe are kept at low for the address access. 5. applicable if oe is brought to low before ce 1r goes low. 6. the t aso , t clol (min) and top (min) are reference values when the access time is determined by t oe . if actual value of each parameter is shorter than specified minimum value, t oe becomes longer by the amount of subtracting actual value from specified minimum value. for example, if actual t aso , t aso (actual) , is shorter than specified minimum value, t aso (min) , during oe control access (i.e., ce 1r stays low) , the t oe becomes t oe (max) + t aso (min) - t aso (actual) . 7. the t aso [ abs ] and t op [ abs ] are the absolute minimum values during oe control access. 8. if actual value of either t clol or t op is shorter than specified minimum value, both t olah and t olch become t rc (min) - t clol (actual) or t rc (min) - t op (actual) . 9. maximum value is applicable if ce 1r is kept at low .
36 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram wrte operations value parameter symbol min. max. unit write cycle time (1) t wc 90 ? ns address setup time (2) t as 0? ns address setup timev t ah 45 ? ns ce 1r write setup time t cs 0 1000 ns ce 1r write hold time t ch 0 1000 ns we setup time t ws 0? ns we hold time t wh 0? ns lb adnd ub setup time t bs 0? ns lb adnd ub hold time t bh -5 ? ns oe setup time (3) t oes 0 1000 ns oe hold time (3,4) t oeh 45 1000 ns oe hold time (5) t oeh ( abs )20?ns oe high to ce 1r low setup time (6) t ohcl -3 ? ns oe high to address hold time (7) t ohah -5 ? ns ce 1r write pulse width (1,8) t cw 60 ? ns we write pulse width (1,8) t wp 60 ? ns ce 1r write recovery time (1,9) t wrc 15 ? ns we write recovery time (1,3,9) t wr 15 1000 ns data setup time t ds 20 ? ns data hold time t dh 0? ns ce 1r high pulse width (9) t cd 20 ? ns notes: 1. minimum value must be equal or greater than the sum of actual t cw (or t wp ) and t wrc (or t wr ) . 2. new write address is valid from either ce 1r or we that is brought to high. 3. maximum value is applicable if ce 1r is kept at low and both we and oe are kept at high. 4. the t oeh is specified from end of t wc (min) , and is a reference value when access time is determined by t oe . if actual value is shorter than specified minimum value, toe becomes longer by the amount of subtracting actual value from specified minimum value. 5. the t oeh [ abs ] is the absolute minimum value if write cycle is terminated by we and ce 1r stay low. 6. t ohcl (min) must be satisfied if read operation is not performed prior to write operation. in case oe is disabled after t ohcl (min) , we low must be asserted after t rc (min) from ce 1r low. in other words, read operation is initiated if t ohcl (min) is not satisfied. 7. applicable if ce 1r stays low after read operation. 8. t cw and t wp are applicable if write operation is initiated by ce 1r and we , respectively. 9. t wrc and t wr are applicable if write operation is terminated by ce 1r and we , respectively. the t wr (min) can be ignored if ce 1r is brought to high together or after we is brought to high. in such a case, the t cp (min) must be satisfied.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 37 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram power down parameter value parameter symbol min. max. unit ce2r low setup time for power down entry t csp 10 ? ns ce2r low setup time after power down entry t c 2 lp 100 ? ns ce 1r high hold time following ce2r high after power down exit t chh 350 ? s ce 1r high setup time following ce2r high after power down exit t chs 10 ? ns psram other timing parameters value parameter symbol min. max. unit ce 1r high to oe invalid for standby entry t chox 20 ? ns ce 1r high to we invalid for standby entry (1) t chwx 20 ? ns ce2r low hold time after power-up (2) t c 2 lh 50 ? s ce2r high hold time after power-up (3) t c 2 hl 50 ? s ce 1r high hold time following ce2r high after power-up (2) t chh 350 ? s input transition time (4) t t 125 ns notes: 1. unintended data may be written into any address location if t chwx is not satisfied. 2. must satisfy t chh (min) after t c2lh (min) . 3. requires power down mode entry and exit after t c2hl . 4. input transition time (t t ) at ac testing is 5 ns as shown below. if actual t t is longer than 5 ns, it may violate some timing parameters of ac specification. psram ac test conditions parameter symbol c onditon value unit input high level v ih v cc r = 2.7v to 3.1v 2.3 v input low level v il v cc r = 2.7v to 3.1v 0.4 v input timing measurement level v ref v cc r = 2.7v to 3.1v 1.3 v input transition time t t between v il and v ih 5ns
38 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram read timing ( oe control access) psram read timing ( ce 1r control access) address valid data input ce 1r oe dq (input) address valid trc tclol tce trc tohah toe valid data input toe top tolch toh tohz tolz tohz toh tolz taso tohah taso address valid address valid data input ce 1r oe dq (input) address valid trc tce trc tchah valid data input toh tchz tclz tchz toh tclz tohah tasc address valid tce tasc tcp note: ce2r and we must be high during read cycle. note: ce2r and we must be high during read cycle.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 39 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram read timing (address access after oe control access) psram read timing (address access after ce 1r control access) address (a19-a2) ce 1r oe dq (input) address valid trc taa trc tohah tohz valid data input valid data in p ut toh tolah toh taso address valid (no change) tax address valid address valid tolz toe address (a1, a0) address (a19-a2) ce 1r dq (input) address valid trc taa trc tchah oe tchz valid data input valid data in p ut toh tclah toh tasc address valid (no change) tax address valid address valid tclz tce address (a1, a0) note: ce2r and we must be high during read cycle. note: ce2r and we must be high during read cycle.
40 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram write timing ( ce 1r control) psram write timing ( we control, single write operation) address valid data input ce 1r oe dq (input) address valid we ub, lb tds tdh tas tas tah twc tbs tohcl tcw twrc twh tws tbh tbs tws address ce 1r dq (input) twc oe valid data input tohz tohcl toes tbs address valid tcs tds tdh twp twr tcp tch tas tbh we ub, lb tohah tas tah note: ce2r must be high during write cycle. note: ce2r must be high during write cycle.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 41 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram write timing ( we control, continuous write operation) psram read / write timing ( ce 1r control) address ce 1r dq (input) twc oe valid data input tohz tohcl toes tbs address valid tcs tds tdh twp twr tas tbh we ub, lb tohah tas tah tbs address ce 1r dq (input) twc oe valid data input tchz twh tohcl tbs write address tws tds tdh tcw twrc tasc tbh we ub, lb tchah tas tah read address tolz tolz toh tclol read data output tcp twh tws note: ce2r must be high during write cycle. note: write address is valid from either ce 1r or we of last falling edge.
42 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram read / write timing ( ce 1r control) psram read / write timing (read = oe control, write = we control) address ce 1r dq oe write data input toeh twh tchz twrc (min) write address tws tce twrc tcp tasc we ub, lb tbh tas trc read address tclz tohcl toh read data output toh twh tws tchah tbs note: ce2r must be high during write cycle. address ce 1r dq twc oe write data input tohz toes tbs write address tds tdh twp twr taso tbh we ub, lb tohah tas tah read address toeh tolz toh read data output low note: ce1r can be tied to low for we and oe controlled operation. when ce 1r is tied to low, output is exclusively controlled by oe .
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 43 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram read / write timing (read = oe control, write = we control) address ce 1r dq oe write data input toeh tohz write address twr toe taso we ub, lb tas trc read address toes tdh read data output toh tbh tolz tohah tbs low note: ce 1r can be tied to low for we and oe controlled operation. when ce 1r is tied to low, output is exclusively controlled o e .
44 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram power down timing psram standby entry timing after read write ce 1r dq tchh tchs tc2lp tcsp ce 2r high - z power down entry power down mode power down exit ce 1r we tchox tchwx oe active (read) standby active (write) standby note: both tchox and tchwx define the earliest entry timing for standby mode. if either of timing is not satis- fied, it takes trc (min) period from either last address transition of a0 and a1, or ce 1r low to high transition.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 45 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram power up timing 2 psram power up timing 1 ce 1r v cc r tc2lh ce2r tchs tchh 0v vccr min ce 1r vccr tc2hl ce2r tchs tchh 0 v vccr min tc2lp tcsp tc2hl note: the tc2lh specifies from ce2r low to high transition after vccr reaches specified minimum level. ce 1r must be brought to high prior to or together with ce2r low to high transition. note: it is recommended ce2r to be kept at low during vccr power-up. the tc2lh specifies after vccr reaches specified minimum level.
46 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? flash erase and programming performance parameter min. max. typ. (1) unit remarks sector erase time ? 0.2 1.0 s excludes programming time prior to erasure word programming time ? 6.0 60 s excludes system-level overhead chip programming time ? ? 200 s excludes system-level overhead erase/program cycle 100,00 ? ? cycle note: 1. test conditions t a = +25 c, v cc = 2.9v, data = checker
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 47 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram data retention switching characteristics symbol parameter conditions min. max. unit v dr vccr data retention supply voltage ce1 r = ce2r v cc r -0.2v or , 2.1 3.1 v ce1 r = ce2r = v ih i dr vccr data retention supply current 2.3 v v cc r 2.7 v, ?1 ma v in = v ih (1) or v il ce1 r = ce2r = v ih (1) , i out = 0 m a i dr 1 vccr data retention supply current 2.3 v v cc r 2.7 v, ?70 a v in 0.2 v or v in v cc r -2.0 v, ce1 r = ce2r v cc r -0.2 v i out = 0 m a t drs data retention setuptime 2.7 v v cc r 3.1 v, 0? ns at data retention entry t drr data retention recoverytime 2.7 v v cc r 3.1 v, 90 ? ns after data retention ? v/ ? t v ccr voltage transition time ? 0.5 ? v/s note: 1. 2.0 v v in v cc r + 0.3 psram data retention timing note: 1. 2.0 v v ih v cc r + 0.3 v 3.1v 2.7v 2.3v 4.0v gnd t drs t drr vccr ce2r ce 1r ce 1r = ce2r >vccr - 0.2v or v ih (1) min data retention mode data bus must be in high-z at data retention entry ? v/ ? t ? v/ ? t
48 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? psram data retention switching characteristics symbol parameter conditions min. max. unit c in input capacitance v in = 0 v 11 14 pf c out output capacitance v out = 0 v 12 16 pf c in 2 control pin capacitance v in = 0 v 14 16 pf c in 3 wp /acc pin capacitance v in = 0 v 21.5 26 pf notes: 1. test conditions t a = +25 c , f = 1.0 mhz i sb 2r vs v in cycle time handling of package: please handle this package carefully since the sides of package created with acute angles. caution: 1) the high voltage (vid) cannot be applied to address pins and control pins except reset. exception is when autoselect and sector group protection function are used. then the high voltage (vid) can be applied to reset. 2) without the high voltage (vid) , sector group protection can be achieved by using ?extended sector group protection? command. 2.5 2.0 1.5 1.0 0.5 0.0 0 200 400 600 800 1000 v in cycle time (ns) i sb2 r vs. v in cycle time (v cc r = 3.0 v) i sb2 r (ma) : rt = 25 c : lt = -30 c : ht = 85 c
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 49 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? k j h g f e d c b a seating plane a b c d e f g h j k 10 9 8 7 6 5 4 3 2 1 ? 0.45 + 0.10/?0.05 (65x) 10 9 8 7 6 5 4 3 2 1 a 1 a e e e1 e d d1 ball grid array ? 65-ball fbga package code: d - 9.0 mm x 9.0 mm body, 0.8 mm ball pitch symbol min. typ. max. units a 1.09 1.19 1.34 mm a1 0.29 0.39 0.49 mm d 8.90 9.00 9.10 mm d1 ? 7.20 ? mm e 8.90 9.00 9.10 mm e1 ? 7.20 ? mm e ? 0.80 ? mm
50 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00a 08/01/02 75v16f64gs16 issi ? ordering information industrial range: -30oc to +85oc sram data boot flash bank flash psram order part no. bus section organization speed(ns) speed(ns) package IS75V16F64GS16-7080DI 16 pc pc 70 80 65-ball fbga

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